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lt3746 1 3746f en/uvlo sync rt ss v cc i set t set scki sdi ldi scko sdo ldo led29 led30 led31 led00 led01 led02 . . . . . . lt3746 100k v in 13v to 42v en v cc 3v to 5.5v v in cap 0.47f gate gnd fb isp isn 4.7f 80.6k 10k c1 2 47f 22h 33m pwmck ttl/cmos 2.048mhz clock ttl/cmos 3746 ta01 10f 46.4k 10nf 60.4k 32.4k typical a pplica t ion descrip t ion 32-channel 20ma led driver with buck controller the lt ? 3746 integrates a 32-channel led driver with a 55v buck controller. the led driver lights up to 30ma/13v of leds in series per channel, and the buck controller gener - ates an adaptive bus voltage supplying the parallel led strings. each channel has individual 6-bit dot correction current adjustment and 12-bit grayscale pwm dimming. both dot correction and grayscale are accessible via a serial data interface in ttl/cmos logic. the lt3746 performs full diagnostic and protection against open/short led and overtemperature fault. the fault status is sent back through the serial data interface. the 30mhz fully-buffered, skew-balanced, cascadable serial data interface makes the chip extremely suitable for large screen lcd dynamic backlighting and mono-, multi-, full-color led displays. 32-channel led driver, 1mhz buck, 3 leds 10ma to 30ma per channel, 500hz 12-bit dimming fea t ures a pplica t ions n 6v to 55v power input voltage range n 32 independent led outputs up to 30ma/13v n 6-bit dot correction current adjustment n 12-bit grayscale pwm dimming n 0.5s minimum led on time n adaptive led bus voltage for high effciency n cascadable 30mhz serial data interface n full diagnostic and protection: individual open/short led an d overtemperature fault n large screen display led backlighting n mono-, multi-, full-color led displays n led billboards and signboards l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners.
lt3746 2 3746f p in c on f igura t ion a bsolu t e maxi m u m r a t ings v in .......................................................................... 57v cap ......................................................... v in C 8v to v in gate .............................................................. cap t o v in led00 to led31, isp, isn ......................................... 13v isp ................................................. isn C 1 v to isn + 1v fb, rt, t set , i set ....................................................... 2v v cc ............................................................... C0.3v to 6v scki, scko, sdi, sdo, ldi, ldo, pwmck, sync, ss, en/uvlo ............................................. C0. 3v to v cc operating junction temperature range (notes 2, 3) ............................................ C40 c to 125c storage temperature range .................. C65 c to 125c (note 1) 19 20 21 22 top view 57 gnd uhh package 56-lead (5mm 9mm) plastic qfn 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 39 40 41 42 43 44 45 46 8 7 6 5 4 3 2 1en/uvlo led15 led14 led13 led12 led11 led10 led09 led08 led07 led06 led05 led04 led03 led02 led01 led00 gnd sync led16 led17 led18 led19 led20 led21 led22 led23 led24 led25 led26 led27 led28 led29 led30 led31 gnd i set t set v in gate cap isp isn fb ss rt scki gnd sdi ldi v cc pwmck ldo sdo gnd scko 38 37 36 35 34 33 32 31 30 29 9 10 11 12 13 14 15 16 17 18 t jmax = 125c, ja = 32c/w, jc = 2.0c/w exposed pad (pin 57) is gnd, must be soldered to pcb or d er in f or m a t ion lead free finish tape and reel part marking* package description temperature range lt3746euhh#pbf lt3746euhh#trpbf 3746 56-lead (5mm 9mm) plastic qfn C40c to 125c lt3746iuhh#pbf lt3746iuhh#trpbf 3746 56-lead (5mm 9mm) plastic qfn C40c to 125c consult ltc marketing for parts specifed with wider operating temperature ranges. *the temperature grade is identifed by a label on the shipping container. consult ltc marketing for information on non-standard lead based fnish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifcations, go to: http://www.linear.com/tapeandreel/
lt3746 3 3746f e lec t rical c harac t eris t ics symbol parameter conditions min typ max units supply v in v in operating voltage l 6 55 v i vin v in supply current v en/uvlo = 0v no switching 0.2 0.4 2 0.55 a ma v cc v cc operating voltage l 3 5.5 v i vcc v cc supply current (note 4) v en/uvlo = 0v led channel off, 30mhz data off led channel on, 30mhz data off led channel on, 30mhz data on 0.1 3.3 10 19 1 3.8 a ma ma ma undervoltage lockout (uvlo) v cc uvlo threshold v cc rising v cc falling 2.82 2.61 2.89 2.68 2.96 2.75 v v en/uvlo shutdown threshold uvlo threshold i vcc <20a v en/uvlo rising v en/uvlo falling 0.35 1.28 1.19 1.31 1.22 1.34 1.25 v v v i en/uvlo en/uvlo bias current v en/uvlo = v cc 0.1 1 a (v in C v cap ) uvlo threshold (v in C v cap ) rising (v in C v cap ) falling 4.6 4.1 4.9 4.4 5.2 4.7 v v soft start (ss) i ss soft start charge current v ss = 1v C16 C12 C8 a soft start discharge current v ss = v cc , v en/uvlo = 1v 330 a v ss(th) soft start reset threshold 0.35 v oscillator v rt rt pin voltage 1.186 1.205 1.224 v i rt rt pin current limit v rt = 0v C80 a f osc oscillator frequency r t = 280k, v in = 12v r t = 105k, v in = 12v r t = 46.4k, v in = 12v 196 490 1000 208 515 1050 220 540 1100 khz khz khz f sync sync frequency range (note 5) r t = 348k, v in = 12v 200 1000 khz sync logic high level voltage low level voltage v in = 12v, v cc = 3v to 5.5v 2.4 0 v cc 0.6 v v error amplifers and loop dynamics v fb fb regulation voltage v isp = v isn = 5v l 1.186 1.210 1.234 v i fb fb input bias current v isp = v isn = 5v, v fb regulated C120 na led regulation voltage v isp = v isn = 5v, v fb = 1v 0.44 0.54 0.64 v t off(min) minimum gate off time v in = 12v, v isp = v isn = 5v, v fb = 1v 120 ns t on(min) minimum gate on time v in = 12v, (v isp C v isn ) = 60mv, v isn = 5v, v fb = 1v 200 ns current sense amplifer isp/isn pin common mode v isp = v isn l 0 13 v v in to isn dropout voltage (v in C v isn ) v in = 12v, v isp = v isn , v fb = 1v l 1.7 2 v current limit sense threshold (v isp C v isn ) v fb = 1v 34 46.5 59 mv i isp isp input bias current C23 a i isn isn input bias current C48 a the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. v in = 24v, v cc = 3.3v, v en/uvlo = 1.5v, v fb = 1.5v, v isp = v isn = 0v, r t = 105k, r iset = 60.4k, c cap = 0.47f to v in , unless otherwise noted.
lt3746 4 3746f symbol parameter conditions min typ max units gate driver v bias cap bias voltage (v in C v cap ) 7v < v in < 55v 6.54 6.77 7.0 0 v i cap cap bias current limit (v in C v cap ) = v bias C 0.5v 22 ma gate high level (v in C v gate ) i gate = C100ma 0.4 v gate low level (v gate C v cap ) i gate = 100ma 0.3 v gate rise time c gate = 3.3nf to v in , v in = 12v 30 ns gate fall time c gate = 3.3nf to v in , v in = 12v 30 ns led driver v iset trimmed i set pin voltage l 1.181 1.205 1.229 v ledxx operating voltage v isp = v isn = v ledxx l 0 13 v ledxx leakage current led channel off, v isp = v isn = 5v, v ledxx = 3v 0.2 a i led led constant sink current v isp = v isn = 5v, v ledxx = 0.5v reg dc = 0x00 reg dc = 0x20 reg dc = 0x3f 7 15 23 10.5 20.5 30 14 26 37 ma ma ma ?i ledc current mismatch between channels v isp = v isn = 5v, v ledxx = 0.5v, reg dc = 0x20 (note 6) 8 15 % ?i ledd current mismatch between devices v isp = v isn = 5v, v ledxx = 0.5v, reg dc = 0x20 (note 7) C15 5 20 % ?i line led current line regulation v isp = v isn = 5v, v ledxx = 0.5v, reg dc = 0x20, v cc = 3v to 5.5v (note 8) C0.2 0.2 0.7 %/v ?i load led current load regulation v isp = v isn = 5v, reg dc = 0x20, v ledxx = 0.5v to 2.5v (note 9) C1 0.7 2 %/v v open open led threshold v isp = v isn = 5v, v ledxx falling 0.1 v v sht short led threshold v isp = v isn = 5v, v ledxx rising 3.65 3.9 4.15 v t ledon minimum led on time v isp = v isn = 5v, reg gs = 0x001 0.5 s pwmck logic high level voltage low level voltage v cc = 3v to 5.5v 2.4 0 v cc 0.6 v v thermal protection i tset t set output current v tset = 1v l 19.0 19.8 20.6 a t set over temperature threshold t a = 25c 510 mv serial data interface v sih v sil single-ended input (note 10) high level voltage low level voltage v cc = 3v to 5.5v 2.4 0 v cc 0.6 v v i si single-ended input current v cc = 3v to 5.5v, si = v cc or gnd C0.2 0.2 a v soh v sol single-ended output (note 10) high level voltage low level voltage v cc = 3v to 5.5v i so = C1ma i so = 1ma v cc C 0.1 0.1 v v v e lec t rical c harac t eris t ics the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. v in = 24v, v cc = 3.3v, v en/uvlo = 1.5v, v fb = 1.5v, v isp = v isn = 0v, r t = 105k, r iset = 60.4k, c cap = 0.47f to v in , unless otherwise noted.
lt3746 5 3746f t i m ing c harac t eris t ics the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. v in = 24v, v cc = 3v to 5.5v, v en/uvlo = 1.5v, v fb = 1.5v, v isp = v isn = 5v, v ledxx = 0.5v, r t = 105k, r iset = 60.4k, c cap = 0.47f to v in , c scko = c sdo = c ldo = 27pf to gnd, unless otherwise noted. symbol parameter conditions min typ max units f scki data shift clock frequency l 30 mhz f pwmck pwmck clock frequency l 25 mhz t wh-cki t w l- c k i scki pulse duration scki = h (figure 3) scki = l (figure 3) l l 16 16 ns ns t wh-pwm t w l- p w m pwmck pulse duration pwmck = h (figure 4) pwmck = l (figure 4) l l 20 20 ns ns t wh-ldi ldi pulse duration ldi = h (figure 3) l 20 ns t su-sdi sdi-scki setup time sdi C scki (figure 3) l 2 ns t hd-sdi scki-sdi hold time scki C sdi (figure 3) l 2 ns t su-ldi scki-ldi setup time scki C ldi (figure 3) l 5 ns t hd-ldi ldi-scki hold time ldi C scki (figure 3) l 15 ns t pd-sck scki-scko propagation delay (rising) scki C scko (figure 3) l 27 44 ns t pd-sck scki-scko propagation delay (falling) scki C scko (figure 3) l 30 50 ns ?t pd-sck sck duty cycle change ?t pd-sck = t pd-sck C t pd-sck C3 ns t pd-sd scko-sdo propagation delay scko C sdo (figure 3) l 2.2 4.5 7 ns t pd-ld ldi-ldo propagation delay (rising) ldi C ldo (figure 3) l 27 44 ns t pd-ld ldi-ldo propagation delay (falling) ldi C ldo (figure 3) l 30 50 ns ?t pd-ld ld duty cycle change ?t pd-ld = t pd-ld C t pd-ld C3 ns t pd-pwm pwmck -led propagation delay pwmck C i led (figure 4) 80 ns t r-so scko/sdo/ldo rise time c load = 27pf, 10% to 90% 3 ns t f-so scko/sdo/ldo fall time c load = 27pf, 90% to 10% 3 ns table 1. test parameter equations ? i ledc (%) = i outn ? i outavg(0 ? 31) i outavg(0 ? 31) ? 100 (1) ? i ledd (%) = i outavg ? i outcal i outcal ? 100 (2) i outcal = 1000 ? 1.205v r iset ? ? ? (3) ? i line (% / v) = i outn vcc = 5.5v ? i outn vcc = 3.0v i outn vcc = 3.0v ? 100 2.5v (4) ? i load (% / v) = i outn voutn = 2.5v ? i outn voutn = 0.5v i outn voutn = 0.5v ? 100 2.0v (5)
lt3746 6 3746f note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the lt3746e is guaranteed to meet performance specifcations from 0c to 125c junction temperature. specifcations over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the lt3746i is guaranteed over the full C40c to 125c operating junction temperature range. note 3: this ic includes thermal shutdown protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 125c when thermal shutdown protection is active. continuous operation above the specifed maximum operating junction temperature may impair device reliability. note 4: the v cc supply current with led channel on highly depends on the led current setting and ledxx pin voltage; its test condition is r iset = 60.4k, reg dc = 0x3f, reg gs = 0xfff, v isp = v isn = 5v, v ledxx = 0.5v. the v cc supply current with serial data interface on highly depends on v cc supply voltage, serial data interface clock frequency, e lec t rical c harac t eris t ics scko/sdo/ldo loading capacitance, and pwmck clock frequency; its test condition is v cc = 3.3v, f scki = 30mhz, c scko = c sdo = c ldo = 27pf, f pwmck = 409.6khz. note 5: the sync frequency must be higher than the rt programmed oscillator frequency, and is suggested to be around 20% higher. any sync frequency higher than the suggested value may introduce sub-harmonic oscillation in the converter due to insuffcient slope compensation. see application information section. note 6: the current mismatch between channels is calculated as equation 1 in table 1. note 7: the current mismatch between devices is calculated as equations 2 and 3 in table 1. note 8: the led current line regulation is calculated as equation 4 in table 1. note 9: the led current load regulation is calculated as equation 5 in table 1. note 10: the specifcations of single-ended input si apply to scki, sdi, and ldi pins; the specifcations of single-ended output so apply to scko, sdo, and ldo pins.
lt3746 7 3746f typical p er f or m ance c harac t eris t ics 200hz two-level dc dimming 200hz four-level dc dimming adaptive led bus voltage i adaptive led bus voltage ii adaptive led bus voltage iii adaptive led bus voltage iv 100hz 8:1 gs dimming 100hz 4096:1 gs dimming 500hz 4096:1 gs dimming t a = 25c, unless otherwise noted. circuit of figure 7: dc 31 = 020, gs 31 = 0200 v pwmck 5v/div v led31 2vdiv v out 2v/div i led31 20ma/div 5ms/div 3746 g01 circuit of figure 7: dc 31 = 020, gs 31 = 0001 v pwmck 5v/div v led31 2vdiv v out 2v/div i led31 20ma/div 500ns/div 3746 g02 circuit of figure 7: dc 31 = 020, gs 31 = 0001 v pwmck 5v/div v led31 2vdiv v out 2v/div i led31 20ma/div 500ns/div 3746 g03 circuit of figure 7: (a) en = 1, gs 31 = 0ff; (b) en = 1, dc 31 = 03f; (c) en = 1, dc 31 = 000 v scki 5v/div v led31 2vdiv v out 2v/div i led31 20ma/div 1ms/div (a) (b) (c) (a) (b) (c) 3746 g04 circuit of figure 7: (a) en = 0, gs 31 = 0fff, (b) en = 1, dc 31 = 03f, (c) en = 1, dc 31 = 000 (d) en = 1, dc 31 = 020 v scki 5v/div v led31 2vdiv v out 2v/div i led31 20ma/div 0.5ms/div (a) (b) (c) (d) 3746 g05 circuit of figure 7: dc 00-31 = 03f, gs 00-31 = 0 fff i load 0.5a/div i l 0.5a/div v out 0.2v/div 2ms/div 3746 g06 circuit of figure 7: dc 00-31 = 020, gs 00-31 = 0800 i load 0.5a/div i l 0.5a/div v out 0.2v/div 2ms/div 3746 g07 circuit of figure 7: dc 00-31 = 03f, gs 00-03 = 01ff, gs 04-07 = 03ff, gs 08-11 = 05ff, gs 12-15 = 07ff, gs 16-19 = 09ff, gs 20-23 = 0bff, gs 24-27 = 0dff, gs 28-31 = 0fff i load 0.5a/div i l 0.5a/div v out 0.2v/div 2ms/div 3746 g08 circuit of figure 7: dc 00-07 = 03f, gs 00-07 = 03ff, dc 08-15 = 02f, gs 08-15 = 07ff, dc 16-23 = 01f, dc 16-23 = 0bff, dc 24-31 = 00f, gs 24-31 = 0fff i load 0.5a/div i l 0.5a/div v out 0.2v/div 2ms/div 3746 g09
lt3746 8 3746f typical p er f or m ance c harac t eris t ics i vcc vs v cc C shutdown mode i vcc vs v cc C channel off, data off i vcc vs v cc C channel on, data off i vcc vs v cc C channel on, data on v cc uvlo threshold vs temperature en/uvlo uvlo threshold vs temperature buck effciency shutdown i vin vs v in quiescent i vin vs v in 0 60 65 efficiency (%) 70 80 75 90 85 100 95 0.1 0.2 0.3 load current (a) 0.4 3746 g10 0.5 0.6 0.7 0.8 0.9 1.0 48v in , 4v out at 200khz 24v in , 12v out at 1mhz 12v in , 4v out at 500khz 0 0 i vin (a) 1 3 2 4 5 10 20 v in (v) 3746 g11 30 40 50 60 t = 25c t = 125c t = ?40c 0 0.38 i vin (ma) 0.39 0.41 0.40 0.42 0.43 10 20 v in (v) 3746 g12 30 40 50 60 t = 25c t = 125c t = ?40c 3.0 0 i vcc (a) 2 6 4 8 10 3.5 4.0 v cc (v) 3746 g13 4.5 5.0 5.5 t = 25c t = 125c t = ?40c ?50 2.60 v cc (v) 2.75 2.70 2.65 2.80 2.85 2.90 ?25 25 50 75 100 125 0 junction temperature (c) 3746 g17 uvlo ? uvlo + ?50 1.20 v en/uvlo (v) 1.26 1.24 1.22 1.28 1.30 1.32 ?25 25 50 75 100 125 0 junction temperature (c) 3746 g18 uvlo ? uvlo + t a = 25c, unless otherwise noted. 3.0 3.05 i vcc (ma) 3.25 3.20 3.15 3.10 3.35 3.30 3.40 3.45 3.5 4.0 v cc (v) 3746 g14 4.5 5.0 5.5 t = 25c t = 125c t = ?40c 3.0 9.95 i vcc (ma) 10.15 10.10 10.05 10.00 10.25 10.20 10.30 10.35 3.5 4.0 v cc (v) 3746 g15 4.5 5.0 5.5 t = 25c t = 125c t = ?40c 3.0 15 i vcc (ma) 21 19 17 23 25 27 3.5 4.0 v cc (v) 3746 g16 4.5 5.0 5.5 t = 25c t = 125c t = ?40c
lt3746 9 3746f typical p er f or m ance c harac t eris t ics fb regulation voltage vs load current led regulation voltage vs load current soft-start charge current i ss vs temperature current sense threshold (v isp - v isn ) vs v isn cap bias voltage (v in - v cap ) vs v in cap bias voltage (v in - v cap ) vs i cap (v in - v cap ) uvlo threshold vs temperature oscillator frequency f osc vs r t oscillator frequency f osc vs temperature ?50 4.40 v in - v cap (v) 4.60 4.50 4.70 4.80 4.90 ?25 25 50 75 100 125 0 junction temperature (c) 3746 g19 uvlo ? uvlo + ?50 480 f osc (khz) 500 490 510 520 ?25 25 50 75 100 125 0 junction temperature (c) 3746 g21 0 1.198 v fb (v) 1.202 1.200 1.204 1.206 1.208 200 400 600 800 1000 load current (ma) 3746 g22 0 0.48 v ledxx (v) 0.49 0.50 0.51 0.52 200 400 600 800 1000 load current (ma) 3746 g23 ?50 ?11.0 i ss (a) ?10.8 ?10.6 ?10.4 ?10.0 ?10.2 ?25 0 25 50 75 100 125 junction temperature (c) 3746 g24 0 45 v isp -v isn (mv) 46 47 49 48 3 6 9 12 15 v isn (v) 3746 g25 t = 25c t = 125c t = ?40c t a = 25c, unless otherwise noted. 20 60 100 180 220 260 0 f osc (khz) 400 200 600 800 1000 140 300 r t (k) 3746 g20 0 6.70 v in -v cap (v) 6.74 6.78 6.90 6.86 6.82 10 20 30 40 50 60 v in (v) 3746 g26 t = 25c t = 125c t = ?40c 0 6.20 v in -v cap (v) 6.30 6.40 6.90 6.80 6.70 6.60 6.50 4 8 12 16 2420 i cap (ma) 3746 g27 t = 25c t = 125c t = ?40c
lt3746 10 3746f typical p er f or m ance c harac t eris t ics led current i led vs led voltage v led led current variation i led vs temperature short led threshold vs v isn t set current vs i set current t set threshold vs temperature led current derating vs temperature v iset pin voltage vs temperature nominal led current vs r iset led current i led vs dot correction ?50 1.200 v iset (v) 1.202 1.210 1.208 1.206 1.204 ?25 0 25 50 75 100 125 junction temperature (c) 3746 g28 4 0 i led (ma) 5 30 25 20 15 10 10 16 22 28 34 40 46 52 58 64 dot correction +1 3746 g30 ?50 17 i led (ma) 23 22 21 20 19 18 ?25 0 25 50 75 100 125 junction temperature (c) 3746 g32 0 0 i tset (a) 20 12 16 8 4 4 8 12 16 20 i iset (a) 3746 g34 ?50 350 450 400 v tset (mv) 700 600 650 550 500 ?25 0 25 50 125 75 100 junction temperature (c) 3746 g35 0 0 v led (v) 12 9 6 3 4 8 12 16 v isn (v) 3746 g33 0 0 i led (ma) 5 35 30 25 20 15 10 0.5 1.0 1.5 2.0 2.5 3.0 v led (v) 3746 g31 dc = 03f dc = 020 dc = 000 80 0 10 5 i led (ma) 35 25 30 20 15 85 90 95 100 120 105 110 115 junction temperature (c) 3746 g36 ot = 0 ot = 1 40 80 0 i led (ma) 4 20 16 12 8 120 160 200 240 280 320 r iset (k) 3746 g29 t a = 25c, unless otherwise noted.
lt3746 11 3746f p in func t ions en/uvlo (pin 1): enable and undervoltage lockout (uvlo) pin. the pin can accept a digital input signal to enable or disable the chip. tie to 0.35v or lower to shut down the chip or tie to 1.34v or higher for normal operation. this pin can also be connected to v in through a resistor divider to program a power input uvlo threshold. if both the enable and uvlo functions are not used, tie this pin to v cc pin. led00 to led31 (pins 2-17, 30-45): led driver output pins. connect the cathodes of led strings to these pins. gnd (pin 18, 20, 27, 29): ground pin. scki (pin 19): serial interface ttl/cmos logic clock input pin. sdi (pin 21): serial interface ttl/cmos logic data input pin. ldi (pin 22): serial interface ttl/cmos logic latch input pin. an asynchronous input signal at this pin latches the serial data in the shift registers into the proper registers and the status information is ready to shift out with the coming clock pulses. see more details in the operation section. v cc (pin 23): logic and control supply pin. the pin powers serial data interface and internal control circuitry. must be locally bypassed with a capacitor to ground. pwmck (pin 24): grayscale pwm dimming ttl/cmos logic clock pin. individual pwm dimming signal is gener - ated by counting this clock pulse from zero to the bits in its 12-bit grayscale pwm register. ldo (pin 25): serial interface ttl/cmos logic latch output pin. sdo (pin 26): serial interface ttl/cmos logic data output pin. scko (pin 28): serial interface ttl/cmos logic clock output pin. sync (pin 46): switching frequency synchronization pin. synchronizes the internal oscillator frequency to an external clock applied to the sync pin. the sync pin is ttl/cmos logic compatible. tie to ground or v cc if not used. rt (pin 47): timing resistor pin. programs the switching frequency from 200khz to 1mhz. see table 2 for the rec - ommended r t values for common switching frequencies. ss (pin 48): soft start pin. placing a capacitor here pro - grams soft start timing to limit inductor inrush current during startup. the soft start cycle will not begin until all the v cc , en/uvlo, and (v in - v cap ) voltages are higher than their respective uvlo thresholds. fb (pin 49): feedback pin. the pin is regulated to the internal bang-gap reference 1.205v during startup and precharging phases. connect to a resistor divider from the buck converter output to program the maximum led bus voltage. see more details in the applications informa - tion section. isn (pin 50): negative inductor current sense pin. the pin is connected to one terminal of the external inductor current sensing resistor and the buck converter output supplying parallel led channels. isp (pin 51): positive inductor current sense pin. the pin is connected to the inductor and the other terminal of the external inductor current sensing resistor. cap (pin 52): v in referenced regulator supply capacitor pin. the pin holds the negative terminal of an internal v in referenced 6.8v linear regulator used to bias the gate driver circuitry. must be locally bypassed with a capacitor to v in . gate (pin 53): gate driver pin. the pin drives an external p-channel power mosfet with a typical peak current of 1a. connect this pin to the gate of the power mosfet with a short and wide pcb trace to minimize trace inductance. v in (pin 54): power input supply pin. must be locally bypassed with a capacitor to ground. t set (pin 55): temperature threshold setting pin. a resistor to ground programs overtemperature threshold. see more details in the applications information section. i set (pin 56): nominal led current setting pin. a resistor to ground programs the nominal led current for all the channels. see more details in the applications informa - tion section. exposed pad (pin 57): ground pin. must be soldered to a continuous copper ground plane to reduce die temperature and to increase the power capability of the device.
lt3746 12 3746f b lock diagra m 48 51 50 46 47 1 23 49 24 22 21 19 c ss c vcc r fb2 r fb1 v cc v cc ss isn rt isp sync 12a en/uvlo fb pwmck ldi sdi ot status info (fault led xx ) x scki scki prechg v ss < 1v (v in - v cap ) v in v in c in r s m1 l d1 gate cap 6.8v 1.205v i set t set v ptat i ref ot uv 1.205v + ? reference bias and uvlo ramp osc s r q + ? + ? + ? r t driver g m1 + ? 53 54 52 c cap c out v out pg por g m2 0.5v led 00 led 01 led 31 en + ? ? . . . ? 28 26 25 ldo sdo scko c0 shift register c1 384 384 32x delay 32x fs fs sdi scko sdo fs en gs register dc register 12-bit pwm dimming constant current sink 6-bit dot correction open/short led 12 12 6 6 fault led xx pwmck i ref led xx gnd 3746 bd (18, 20, 27, 29, exposed pad 57) 56 55 + ? + ? r iset r tset s r q
lt3746 13 3746f opera t ion the lt3746 integrates a single constant-frequency current- mode nonsynchronous buck controller with thirty-two linear current sinks. the buck controller generates an adaptive output led bus voltage to supply parallel led strings and the thirty-two linear current sinks regulate and modulate individual led strings. its operation is best understood by referring to the block diagram. start-up the lt3746 enters shutdown mode and drains almost zero current when the en/uvlo pin is lower than 0.35v. once the en/uvlo pin is above 0.35v, the part starts to wake up internal bias currents, generate various references, and charge the capacitor c cap towards 6.8v regulation voltage. this v in referenced voltage regulator (v in - v cap ) will supply the internal gate driver circuitry driving an external p-channel mosfet in normal operation. the lt3746 remains in undervoltage lockout (uvlo) mode as long as any one of the en/uvlo, v cc , and (v in - v cap ) uvlo fags is high. their uvlo thresholds are typically 1.31v, 2.89v, and 4.9v, respectively. after all the uvlo fags are cleared, the buck controller starts to switch, and the soft start ss pin is released and charged by a 12a current source, thereby smoothly ramping up the inductor current and the output led bus voltage. power-on-reset (por) during start-up, an internal power-on-reset (por) high signal blocks the input signals to the serial data interface and resets all the internal registers except the 386-bit shift register. the 1-bit frame select (fs) register, 1-bit enable led channel (en) register, individual 12-bit grayscale (gs) registers, and individual 6-bit dot correction (dc) registers are all reset to zero. thus all the led channels are turned off initially with the default grayscale (0x000) and dot correction (0x00) setting. once the part completes its soft start (i.e., the ss pin voltage is higher than 1v) and the output led bus voltage is power good (i.e., within 5% of its fb programmed regulation level), the por signal goes low to allow the input signals to the serial data interface. any fault triggering the soft start will generate another por high signal and reset internal registers again. serial data interface the lt3746 has a 30mhz, fully-buffered, skew-balanced, cascadable serial data interface. the interface uses a novel 6-wire (ldi, scki, sdi, ldo, scko, and sdo) topology and can be connected to microcontrollers, digital signal processors (dsps), or feld programmable gate arrays (fpgas). in a conventional 4-wire topology shown in figure 1, the ldi and scki signals need global routing while the sdi signal only needs local routing between chips. depending on the number of chips in cascade and the size of system pcb board, external clock-tree type buffers with corresponding driving capability are needed for both the ldi and scki signals to minimize signal skews. the propagation delay caused by the buffer insertion on the scki signal yields the clock skew between the scki and sdi signals, which usually requires the customer end to balance it. since both the sdi and sdo signals require the same scki signal to send and receive, the propagation delay between the sdi and sdo signals limits the number of chips in cascade and the series data interface clock frequency. the novel 6-wire topology eliminates the need for global routing and buffer insertion for the ldi and scki signals. instead, it provides the ldo and scko signals along with the sdo signal to drive the next chip. the skew inside the chip among the ldi, scki, and sdi signals is balanced internally. the skew outside the chip among the ldo, scko, and sdo signals can be easily balanced by parallel routing these three signals between chips. the sdi signal is sent with the scki signal, and the sdo signal is received with the scko signal. a slight duty cycle change between the scki and scko signals may occur due to the process variation, supply voltage and operating temperature. this duty cycle change results from the difference in propagation delays of the positive and negative edges of the scki/scko signals and will affect the maximum number of cascadable chips, depending on the scki speed. in summary, the 6-wire topology extends the maximum number of cascadable chips, boosts the series data interface clock frequency, eliminates the need for buffer insertion for global signals, and offers an easy pcb layout. in a low-speed application with a small number of cascaded chips, the 6-wire topol - ogy can be simplifed to the 4-wire topology by ignoring the ldo and scko outputs.
lt3746 14 3746f opera t ion ldo scko sdo controller lt3746 6-wire topology sdi scki ldi ldo scko sdo ldi scki sdi chip 1 ldo scko sdo ldi scki sdi chip 2 ldo scko sdo ldi scki sdi chip n ldo scko sdo controller conventional 4-wire topology sdi 3746 f01 ldo scko sdo ldi scki sdi chip 1 ldo scko sdo ldi scki sdi chip 2 ldo scko sdo ldi scki sdi chip n figure 1. lt3746 6-wire topology vs conventional 4-wire topology command register: c1: enable led channels - enable = 1, disable = 0 c0: frame select - gs frame = 0, dc frame = 1 status register: s0-s31: led 0-31 fault - fault = 1, ok = 0 f0: ot - over temperature = 1, ok = 0 386 bits gs frame gs 0, 12 bits dc 0, 6 bits dc 31, 6 bits dc 0, 6 bits dc 31, 6 bits 3746 f02 gs 31, 12 bits lsb lsb lsb lsb lsb lsb msb msb msb msb msb msb c0c1 dc frame c0c1 x x x x x x s0 0 0 0 0 0 s31 0 0 0 0 0 x x x x x x status frame f00 figure 2. serial data frame format
lt3746 15 3746f opera t ion figure 4. grayscale pwm dimming and precharging signal timing chart figure 3. serial data input and output timing chart pwmck 4096 4095 1 2 3584 1 2 3 c1/en i(led00) reg = 0x002 reg = 0xfff tracking phase precharging phase reg = 0x000 i(led01) t wh-pwm t wl-pwm t pd-pwm i(led31) prechg 3585 3746 f04 scki 378 1 378 input data status data 385 1 385 384 386 3746 f03 386 385 384 385 386 1 c0 = 0 c0 = 1 c1 c0 = 1 f0 c1 0 x f0 c1 c1 gs 0 lsb c0 = 0 f0 c1 gs 0 lsb gs 31 msb gs 31 msb c1 f0 0 gs 0 lsb gs 0 lsb + 1 gs 31 msb gs 31 msb dc 0 lsb dc 0 lsb dc 0 lsb + 1 dc 31 msb dc 31 msb 386 1 1 sdi ldi sr[1] ldo sr[0] scko sdo/ sr[385] t wh-ldi t hd-ldi t su-ldi t wh-cki t wl-cki t su-sdi t hd-sdi t pd-ld t pd-ld t pd-sck t pd-sck t pd-sd dc 31 msb dc 31 msb dc 31 msb ? 1 gs 31 msb dc 31 msb f0 0
lt3746 16 3746f pwm 1 pwm 2 pwm 3 prechg ideal v out lt3746 v out constant v out 4096*t pwmck 4.4v 4.4v 4.0v 3.6v t 1 t 2 t 3 t 4 4.4v 4.0v 3.6v 3.1v (1) v out = 4.4v 3746 f05 (2) (3) 1.3v 0.9v 0.5v ? ? ? + ? + ? + + ? + + 3.5v 3.9v opera t ion figure 2 shows two serial data input sdi frames (gs frame and dc frame) and one serial data output sdo frame (status frame). all the frames have the same 386-bit in length and are transmitted with the msb frst and the lsb last. the sdi frames are sent with the scki signal and the sdo frame is received with the scko signal. the c0 bit (frame select) determines any sdi frame to be either a gs frame (c0 = 0) or a dc frame (c0 = 1), and the c1 bit (en) enables (c1 = 1) or disables (c1 = 0) all the led channels. the status frame reads back the t set pin resistor-programmable over- temperature fag and individual open/short led fault fags, as well as the individual 6-bit dc setting. inside the part, there are one 386-bit shift register sr[0:385], one 1-bit frame select (fs) register, one 1-bit enable led channel (en) register, thirty-two 12-bit gray - scale (gs) registers, thirty-two 6-bit dot correction (dc) registers, one 1-bit over temperature (ot) fag register, and thirty-two 1-bit led fault fag registers. the input of the 386-bit shift register, i.e., the input of the frst bit sr[0], is connected to the sdi signal. the output of the 386-bit shift register, i.e., the output of the last bit sr[385] is con - nected to the sdo signal. the scki signal shifts the sdi frame (gs or dc frame) in and the scko signal shift the sdo frame (status frame) out of the 386-bit shift register with their rising edges. the ldi high signal latches the sdi frame (gs or dc frame) from the 386-bit shift register into corresponding fs, en, gs or dc registers, and loads the sdo frame (status frame) from the ot and led fault fag registers to the 386-bit shift register at the same time. the ldo signal is a buffered version of the ldi signal with certain delay added to match the delay between the scki and scko signals. therefore, a daisy-chain type loop communication with simultaneous writing and reading capability is implemented. figure 3 illustrates the timing relation among serial input and serial output signals in more detail. one dc frame fol - lowed by another gs frame is sent through the ldi, scki, and sdi signals. at the same time, two status frames are received through the ldo, scko, and sdo signals. the rising edges of the scki signal shift a frame of 386-bit data at the sdi pin into the 386-bit shift register sr[0:385]. after 386 clock cycles, all the 386-bit data sit in the right place waiting for the ldi signal. an asynchronous ldi high signal latches the 1-bit fs register, 1-bit en register, and individual 12-bit gs registers (when fs = 0) or 6-bit dc registers (when fs = 1) for each channel. at the same time, a frame of status information, including over temperature fag and individual open/short led fault fags, is parallel loaded into the 386-bit shift register and will be shifted out with the coming clock cycles. constant current sink each led channel has a local constant current sink regu - lating its own led current independent of the led bus voltage v out . the recommended led pin voltage ranges from 0.5v to 2.5v. as shown in the typical performance characteristics i led vs v led curves, the led current i led has the best load regulation when the led pin voltage v led sits between 0.5v to 2.5v. a lower led bus voltage v out may not regulate all the led channels across tempera - ture, current, and manufacturing variation, while a higher figure 5. adaptive-tracking-plus-precharging led bus voltage technique
lt3746 17 3746f led bus voltage v out will force a higher led pin voltage across the current sink, thereby dissipating more power inside the part. see more details about the choice of the led bus voltage and the power dissipation calculation in the application information section. dot correction and grayscale digital-to-analog conversion the resistor on the i set pin programs the nominal led current (4ma to 20ma) for all the channels. individual led channel can be adjusted to a different current setting by its own 6-bit dot correction register. the adjustable led current ranges from 0.5x to 1.5x of the nominal led current in 63 linear steps. see more details about setting nominal led current and dot correction in the applications information section. in addition to the dot correction current adjustment, individual led channels can also be modulated by their own grayscale pwm dimming signal. to achieve a better performance, all the grayscale pwm dimming signals are synchronized to the same frequency with no phase shift between rising edges. each constant current sink is enabled or disabled when its grayscale pwm dimming signal goes high or low. this periodic grayscale pwm dimming signal is generated by its own 12-bit grayscale register with a duty cycle from 0/4096 to 4095/4096 and a period equal to 4096 pwmck clock cycles. the generation of the grayscale pwm dimming signal is best understood by referring to figure 4. after en = 1 is set, the frst rising edge of the pwmck signal will in - crease the internal 12-bit grayscale counter from zero to one and turn on all the led channels with grayscale value not zero. each following rising edge of the pwmck signal increases the grayscale counter by one. any led channel will be turned off when its 12-bit grayscale register value is equal to the value in the grayscale counter. to generate a 100% duty cycle for all the grayscale pwm dimming signals, the pwmck signal can be paused before counting to the value in any individual 12-bit grayscale registers. setting en = 0 will reset the grayscale counter to zero and turn off all the led channels immediately. dual-loop analog or control the switching frequency can be programmed from 200khz to 1mhz with the resistor connected to the rt pin and it can be synchronized to an external clock using the sync pin. each switching cycle starts with the gate driver turning on the external p-channel mosfet m1 and the inductor current is sampled through the sense resistor r s between the isp and isn pins. this current is amplifed and added to a slope compensation ramp signal, and the resulting sum is fed into the positive terminal of the pwm comparator. when this voltage exceeds the level at the negative terminal of the pwm comparator, the gate driver turns off m1. the level at the negative terminal of the pwm comparator is set by either of two error amplifers g m1 and g m2 . in this dual-loop analog or control, the fb loop g m1 regulates the fb pin voltage to 1.205v and the led loop g m2 regulates the minimum active led pin voltage (led00 to led31) to 0.5v. in the startup phase, the g m2 is disabled and the output led bus voltage is regulated towards the feedback resistor programmed led bus volt - age. this fb programmed voltage defnes the maximum led bus voltage and should be programmed high enough to supply the worst case led string across temperature, current, and manufacturing variation. adaptive-tracking-plus-precharging higher system effciency and faster transient response are two highly anticipated specifcations in an indi - vidually-modulated multi-channel led driver chip. the lt3746 uses a patent pending adaptive-tracking- plus-precharging technique to achieve both of them simultaneously. besides 32 internal grayscale pwm dimming signals, the part also generates another internal precharging signal prechg. as shown in figure 4, the prechg signal divides any grayscale pwm dimming cycle into two phases: tracking phase when prechg = 0 and precharging phase when prechg = 1. during each grayscale pwm dimming cycle C 4096 pwmck clock cycles, the prechg signal stays low for the frst 3584 clock cycles (7/8 of the grayscale pwm dimming opera t ion
lt3746 18 3746f period) and goes high for the rest 512 clock cycles (1/8 of the grayscale pwm dimming period). in the event of all the led channels being not active (i.e., either fault or off) before the 3585th pwmck clock, the prechg signal will go high immediately. to better explain the operation of the adaptive-tracking- plus-precharging technique, a simplifed application system with 3-channel led array is presented in figure 5. each channel consists of a single led with the forward voltage drop equal to 3.1v, 3.5v, and 3.9v, respectively. three internal grayscale pwm dimming signals pwm1, pwm2, and pwm3 are used to modulate each led channel. at the beginning of each grayscale pwm dimming cycle, all three led channels are turned on and the tracking phase starts with prechg = 0. the amplifer g m2 is enabled and takes the control from the amplifer g m1 , regulating the minimum active led pin voltage to 0.5v. with the v led3 equal to 0.5v, the output led bus voltage is tracked to 4.4v. subsequently, at a certain time instant t 1 when the third channel is turned off, the minimum active led pin voltage goes to v led2 , 0.9v. then the amplifer g m2 tracks the output led bus voltage down to 4v to maintain the minimum active led pin voltage opera t ion equal to 0.5v again. similarly at the next time instant t 2 , the output led bus voltage is tracked down to 3.6v. in this manner, the adaptive-tracking technique eliminates unnecessary power dissipation across the current sinks and yields superior system effciency when compared to a constant 4.4v output voltage. at a later time instant t 3 when the prechg signal goes high, the amplifer g m2 is disabled and gives the control back to the amplifer g m1 . the amplifer gm1 regulates the output led bus voltage towards the fb programmed maximum value 4.4v to guarantee shorter minimum led on-time for the next grayscale pwm dimming cycle. without the precharging phase, the output led bus voltage will stay at 3.6v before the next grayscale pwm dimming cycle, when all the 3 led channels will be turned on again. at that time the 3.6v led bus voltage is too low to keep all the led channels in regulation, and the minimum led on time is greatly increased to accommodate the slow transient response of the switch - ing buck converter charging the output capacitor from 3.6v to 4.4v. this adaptive-tracking-plus-precharging led bus voltage technique simultaneously lowers the power dissipation in the lt3746 and maintains a shorter minimum led on-time.
lt3746 19 3746f a pplica t ions i n f or m a t ion globally, the lt3746 converts a higher input voltage to a single lower led bus voltage (v out ) supplying 32 parallel led strings with the adaptive-tracking-plus-precharging technique. locally, the part regulates and modulates the current of each string to an independent dot correction and grayscale pwm dimming setting sent by ttl/cmos logic serial data interface. this application information section serves as a guideline of selecting external components (refer to the block diagram) and avoiding common pitfalls for the typical application. programming maximum v out the adaptive-tracking-plus-precharging technique regu - lates v out to its maximum value during the startup and precharging phases, and adaptively lowers the voltage to keep the minimum active led pin voltage around 0.5v during the tracking phase. therefore, the maximum v out should be programmed high enough to keep all the led pin voltages higher than 0.5v to maintain led current regulation across temperature, current, and manufactur - ing variation. as a starting point, the maximum led bus voltage, v out(max) , can be calculated as: v out(max) = 0.5v + n ? v f(max) where n is the number of led per string and v f(max) is the maximum led forward voltage rated at the highest operating current and the lowest operating temperature. the v out(max) is programmed with a resistor divider between the output and the fb pin. the resistor values are calculated as: r fb2 = r fb1 v out(max) 1.205v - 1 ? ? ? tolerance of the feedback resistors will add additional errors to the output voltage, so 1% resistor values should be used. the fb pin output bias current is typically 120na, so use of extremely high value feedback resistors could also cause bias current errors. a typical value for r fb1 is 10k. v in power input supply range the power input supply for the lt3746 can range from 6v to 55v, covering a wide variety of industrial power supplies. another restriction on the minimum input voltage v in(min) is the 2v minimum dropout voltage between the v in and isn pins, and thus the v in(min) is calculated as: v in(min) = v out(max) + 2v choosing switching frequency selection of the switching frequency is a tradeoff between effciency and component size. low frequency operation improves effciency by reducing mosfet switching losses and gate charge losses. however, lower frequency opera - tion requires larger inductor and capacitor values. another restriction on the switching frequency comes from the input and output voltage range caused by the minimum switch on and switch off time. the highest switching frequency f sw(max) for a given application can be calculated as: f sw(max) = min d min t on(min) , 1? d max t off(min) ? ? ? ? ? ? ? ? where the minimum duty cycle d min and the maximum duty cycle d max are determined by: d min = v out(min) + v d v in(max) + v d and d max = v out(max) + v d v in(min) + v d t on(min) is the minimum switch on time (~200ns), t off(min) is the minimum switch off time (~120ns), v out(min) is the minimum adaptive output voltage, v in(max) is the maxi - mum input voltage, and v d is the catch diode forward volt - age (~0.5v). the calculation of f sw(max) simplifes to: f sw(max) = min 5 ? v out(min) + v d v in(max) + v d , 8.33 ? v in(min) ? v out(max) v in(min) + v d ? ? ? ? ? ? ? ? mhz obviously, lower frequency operation accommodates both extremely high and low v out to v in ratios. besides these common considerations, the specifc application also plays an important role in switching fre - quency choice. in a noise-sensitive system, the switching
lt3746 20 3746f a pplica t ions i n f or m a t ion frequency is usually chosen to keep the switching noise out of a sensitive frequency band. switching frequency setting and synchronization the lt3746 uses a constant switching frequency that can be programmed from 200khz to 1mhz with a resistor from the rt pin to ground. table 2 shows r t values for common switching frequencies. table 2. switching frequency f sw vs r t value f sw (khz) r t * (k) 200 280 300 182 400 133 500 105 600 84.5 700 71.5 800 60.4 900 53.6 1000 46.4 * recommend 1% standard values synchronizing the lt3746 oscillator to an external fre - quency can be achieved using the sync pin. the square wave amplitude, compatible to ttl/cmos logic, should have valleys that are below 0.6v and peaks that are above 2.4v. the synchronization frequency also ranges from 200khz to 1mhz, in which the r t resistor should be chosen to set the internal switching frequency around 20% below the synchronization frequency. in the case of 200khz synchronization frequency, r t = 348k is recommended. it is also important to note that when the synchroniza - tion frequency is much higher than the r t programmed internal frequency, the internal slope compensation will be signifcantly reduced, which may trigger sub-harmonic oscillation at duty cycles greater than 50%. inductor current sense resistor r s and current limit the current sense resistor, r s , monitors the inductor current between the isp and isn pins, which are the in - puts to the internal current sense amplifer. the common mode input voltage of the current sense amplifer ranges from 0v to (v in C 2v) or 13v absolute maximum value, whichever is lower. the current sense amplifer not only provides current information to form the current-mode control, but also a 46.5mv threshold. the 46.5mv threshold across the r s resistor imposes an accurate current limit to protect both p-channel mosfet m1 and catch diode d1, and also to prevent inductor current saturation. good kelvin sensing is required for accurate current limit. the r s resistor value can be determined by: i out(max) = i l(max) ? ? i l 2 where the maximum inductor current i l(max) is set by: i l(max) = 46.5mv r s i out(max) is the maximum output load current, and ?i l is the inductor peak-to-peak ripple current. allowing ad - equate margin for ripple current and external component tolerances, r s can be estimated as: r s = 35mv i out(max) inductor selection the critical parameters for selection of an inductor are inductance value, dc or rms current, saturation current, and dcr resistance. for a given input and output voltage, the inductor value and switching frequency will determine the peak-to-peak ripple current, ?i l . the ?i l value usually ranges from 20% to 50% of the maximum output load current, i out(max) . lower values of ?i l require larger and more costly inductors; higher values of ?i l increase the peak currents and the inductor core loss. an inductor current ripple of 30% to 40% offers a good compromise between inductor performance and inductor size and cost. however, for high duty cycle applications, a ?i l value of ~20% should be used to prevent sub-harmonic oscillation due to insuffcient slope compensation.
lt3746 21 3746f a pplica t ions i n f or m a t ion the largest inductor ripple current occurs at the highest v in . to guarantee that the ripple current stays below the specifed maximum, the inductor value should be chosen according to the following equation: l v out + v d v in(max) + v d ? v in(max) ? v out f sw ? ? i l the inductor dc or rms current rating must be greater than the maximum output load current i out(max) and its saturation current should be higher than the maximum inductor current i l(max) . to achieve high effciency, the dcr resistance should be less than 0.1, and the core material should be intended for high frequency applications. power mosfet selection important parameters for the external p-channel mosfet m1 include drain-to-source breakdown voltage (v (br)dss) , maximum continuous drain current (i d(max) ), maximum gate-to-source voltage (v gs(max) ), total gate charge (q g ), drain-to-source on resistance (r ds(on) ), reverse transfer capacitance (c rss ). the mosfet v (br)dss specifcation should exceed the maximum voltage across the source to the drain of the mosfet, which is v in(max) plus v d . the i d(max) should exceed the peak inductor current, i l(max) . since the gate driver circuit is supplied by the internal 6.8v v in referenced regulator, the v gs(max) rating should be at least 10v. each switching cycle the mosfet is switched off and on, a packet of gate charge q g is transferred from the v in pin to the gate pin, and then from the gate pin to the cap pin. the resulting dq g /dt is a current that must be sup - plied to the c cap capacitor by the internal regulator. the maximum 20ma current capability of the internal regulator limits the maximum q g(max) it can deliver to: q g(max) = 20ma f sw therefore, the q g at v gs = 6.8v from the mosfet data sheet should be less than q g(max) . for maximum effciency, both r ds(on) and c rss should be minimized. lower r ds(on) means less conduction loss while lower c rss reduces transition loss. unfortunately, r ds(on) is inversely related to c rss . thus balancing the conduction loss with the transition loss is a good criterion in selecting a mosfet. for applications with higher v in voltages (24v) a lower c rss is more important than a low r ds(on) . catch diode selection the catch diode d1 carries load current during the switch off time. important parameters for the catch diode includes peak repetitive reverse voltage (v rrm ), forward voltage (v f ), and maximum average forward current (i f(av) ). the diode v rrm specifcation should exceed the maximum reverse voltage across it, i.e., v in(max) . a fast switching schottky diode with lower v f should be used to yield lower power loss and higher effciency. in continuous conduction mode, the average current conducted by the catch diode is calculated as: i d(avg) = i out ? (1? d) the worst-case condition for the diode is when v out is shorted to ground with maximum v in and maximum i out at present. in this case, the diode must safely conduct the maximum load current almost 100% of the time. to improve effciency and to provide adequate margin for short circuit operation, a schottky diode rated to at least the maximum output current is recommended. c in , c vcc , and c cap capacitor selection a local input bypass capacitor c in is required for buck converters because the input current is pulsed with fast rise and fall times. the input capacitor selection criteria are based on the voltage rating, bulk capacitance, and rms current capability. the capacitor voltage rating must be greater than v in(max) . the bulk capacitance determines the input supply ripple voltage and the rms current capability is used to keep from overheating the capacitor.
lt3746 22 3746f a pplica t ions i n f or m a t ion the bulk capacitance is calculated based on maximum input ripple, ?v in : c in = d max ? i out(max) ? v in ? f sw ?v in is typically chosen at a level acceptable to the user. 100mv is a good starting point. for ceramic capacitors, only x5r or x7r type should be used because they retain their capacitance over wider voltage and temperature ranges than other types such as y5v or z5u. aluminum electrolytic capacitors are a good choice for high voltage, bulk capacitance due to their high capacitance per unit area. the capacitor rms current is: i cin(rms) = i out ? v out ? ( v in ? v out ) v in 2 if applicable, calculate at the worst case condition, v in =2 ? v out . the capacitor rms current rating speci - fed by the manufacturer should exceed the calculated i cin(rms) . due to their low esr, ceramic capacitors are a good choice for high voltage, high rms current han - dling. note that the ripple current ratings from aluminum electrolytic capacitor manufacturers are based on 2000 hours of life. this makes it advisable to further derate the capacitor or to choose a capacitor rated at a higher temperature than required. for a larger high voltage capacitor value, the combination of aluminum electrolytic capacitors and ceramic capacitors is an economical approach. multiple capacitors may also be paralleled to meet size or height requirements in the design. locate the capacitor very close to the mosfet switch and the catch diode, and use short, wide pcb traces to minimize parasitic inductance. the general discussion above also applies to the capacitor c vcc at the v cc pin and the capacitor c cap between the v in and cap pins. typically, a 10f 10v-rated ceramic capaci - tor for c vcc and a 0.47f 16v-rated ceramic capacitor for c cap should be suffcient. c out capacitor selection the output capacitor has two essential functions. along with the inductor, it flters the square wave generated by the lt3746 to produce the dc output containing a con - trolled voltage ripple. it also stores energy to satisfy load transients and to stabilize the dual-loop operation. thus the selection criteria for c out are based on the voltage rating, the equivalent series resistance esr, and the bulk capacitance. as always, choose the c out with a voltage rating greater than v out(max) . the lt3746 utilizes the output as the dominant pole to sta - bilize the dual loop operation, so the c out value determines the unity gain frequency f ugf , which is set around 1/10 of the switching frequency. to stabilize the fb loop during the startup and precharging phases and the led loop during the tracking phase, a low-esr capacitor (tens of m) should be used and its minimum c out is calculated as: c out = max 0.25 r s ? f ugf , 1.5 v out(max) ? r s ? f ugf ? ? ? ? ? ? ? ? the ad aptive-tracking-plus-precharging technique moves the v out with the grayscale pwm dimming frequency to improve system effciency, choosing a ceramic capacitor as the c out inevitably generates acoustic noise due to the piezo effect of the ceramic material. in an acoustic noise sensitive application, low esr tantalum or aluminum capacitors are preferred. when choosing a capacitor, look carefully through the data sheet to fnd out what the actual capacitance is under operating conditions (applied voltage and temperature). a physically larger capacitor, or one with a higher voltage rating, may be required.
lt3746 23 3746f undervoltage lockout (uvlo) and shutdown lt3746 has three uvlo thresholds with hysteresis for the en/uvlo, v cc , and cap pins. the part will remain in uvlo mode not switching until all the en/uvlo, v cc , and (v in - v cap ) voltages pass their respective typical thresh - olds (1.31v, 2.89v, and 4.9v). as shown in figure 6, the en/uvlo pin can be controlled in two different ways. the en/uvlo pin can accept a digital input signal to enable or disable the chip. tie to 0.35v or lower to shut down the chip or tie to 1.34v or higher for normal operation. this pin can also be connected to a resistor divider between v in and ground to program a power input v in uvlo threshold. after r uv1 is selected, r uv2 can be calculated by: r uv2 = r uv1 ? v in(on) 1.31v ? 1 ? ? ? ? ? ? where v in(on) is the power input voltage above which the part goes into normal operation. it is important to check the en/uvlo pin voltage not to exceed its 6v absolute maximum rating: v in(max) ? r uv1 r uv1 + r uv2 < 6v soft-start during soft-start, the ss pin voltage smoothly ramps up inductor current and output voltage. the effective voltage range of ss pin is from 0v to 1v. therefore, the typical soft-start period is t ss = c ss ? 1v 12a where c ss is the capacitor connected at ss pin and 12a is the soft-start charge current. whenever a uvlo or thermal shutdown occurs, the ss pin will be discharged and the part will stop switching until the uvlo event has disappeared and the ss pin has reached it reset threshold, 0.35v. the part then initiates a new soft-start cycle. a pplica t ions i n f or m a t ion setting nominal led current the nominal led current is defned as the average led current across 32-channel when all the individual dot cor - rection registers are set to 0x20. the nominal led current is programmed by a single resistor, r iset , between the i set pin and ground. the voltage at the i set pin, v iset , is trimmed to an accurate 1.205v, generating a current inversely proportional to r iset . the nominal led current, i led(nom) , can be calculated as: i led(nom) = v iset r iset ? 1000 i led(nom) must be set between 4ma and 20ma. typical r iset resistor values for various nominal led currents are listed in table 3. table 3. nominal led current i led(nom) vs. r iset value i led(nom) (ma) r iset * (k) 4 301 10 121 15 80.6 20 60.4 * recommend 1% standard values setting dot correction the lt3746 can adjust the led current for each channel independently. this fne current adjustment, also called dot correction, is mainly used to calibrate the brightness deviation between led channels. the 6-bit (64 steps) dot figure 6. methods of controlling the en/uvlo pin v in v cc en/uvlo from controller (a) (b) 3746 f06 v in v cc en/uvlo v in r uv2 r uv1
lt3746 24 3746f correction setting adjusts each led current from 0.5x to 1.5x of the nominal led current according to: i ledn = i led(nom) ? dc n + 32 64 ? ? ? ? ? ? where i ledn is the nth led current and dc n is the nth programmed dot correction setting (dc n = 0 to 63). the fne current step over the nominal led current gives an excellent resolution: ? i led i led(non) = 1 64 1.56% which enhances the relative led current match accuracy if used as calibration. setting grayscale although adjusting the led current changes its luminous intensity, or brightness, it will also affect the color match - ing between led channels by shifting the chromaticity coordinate. the best way to adjust the brightness is to control the amount of led on/off time by pulse width modulation (pwm). the lt3746 can adjust the brightness for each channel independently. the 12-bit grayscale pwm dimming results in 4096 linear brightness steps from 0% to 99.98%. the brightness level gs n % for channel n can be calculated as: gs n % = gs n 4096 ? 100% where gs n is the nth programmed grayscale setting (gs n = 0 to 4095). open/short led fault the lt3746 has individual led fault diagnostic circuitry that detects both open and short led faults for each channel. the open led fault is defned as any led string is open or disconnected from the circuit; and the short led fault is defned as any led string is shorted across itself. the open led fag is set if the led pin voltage is lower than 0.1v (typical) during on status with initial 500ns blanking. the short led fag is set if the led pin voltage is higher than 75% of the led bus voltage v out any time. if one led channel is shorted across itself, the channel will be turned off to eliminate unnecessary power dissipation. the function can also be used to disable led channels by connecting their led pins to the output directly. both the open and short led fags are combined to set the led fault bits (s0 to s31) in the status frame to 1. thermal protection the lt3746 has two over temperature thresholds: one is the fxed internal thermal shutdown and the other one is programmed by a resistor, r tset , between the t set pin and ground. when the junction temperature exceeds 165c, the part will enter thermal shutdown mode, shut down serial data interface, turn off led channels, and stop switching. after the junction temperature drops below 155c, the part will initiate a new soft start. when the r tset is placed at the t set pin, a current equal to the current fowing through the r iset passes the r tset , generating a voltage v tset at the t set pin, which is calculated as: v tset = 1.205v ? r tset r iset a pplica t ions i n f or m a t ion
lt3746 25 3746f then the v tset is compared to an internal proportional- to-absolute-temperature voltage v ptat , v ptat = 1.72mv ? (t j + 273.15) where t j is the lt3746 junction temperature in c. when v ptat is higher than v tset , an overtemperature fag ot = 1 is set. once the r tset programmed temperature is exceeded, the part will also gradually derate the nominal led current i led(nom) to limit the total power dissipation without interrupting its normal operation. cascading devices and determining serial data interface clock in a large lcd backlighting or led display system, mul - tiple lt3746 chips can be easily cascaded to drive all the led strings. the lt3746 adopts a 6-wire topology, which balances the internal clock skew and matches the external trace capacitance with an easy pcb layout. the minimum serial data interface clock frequency f scki for a large display system can be calculated as: f scki = n lt3746 ? 386 ? f refresh a pplica t ions i n f or m a t ion where n lt3746 is the number of lt3746 chips and f refresh is the refresh rate of the whole system. calculating power dissipation the total power dissipation inside the chip can be calcu- lated as: p total = v in ? (i vin + f sw ? q g ) + v cc ? i vcc + gs n % ? i ledn ? v ledn n = 0 31 where i vin is the power input v in quiescent current, i vcc is the v cc supply current, and v ledn is the led pin volt - age for channel n. from the total power dissipation p total , the junction temperature t j can be calculated as: t j = t a + p total ? ja keep t j below the maximum operating junction tempera - ture 125c.
lt3746 26 3746f typical a pplica t ion figure 7. 32-channel led driver, 500khz buck, 1 led 10ma to 30ma per channel, 100hz 12-bit dimming en/uvlo sync rt ss v cc i set t set scki sdi ldi scko sdo ldo led26 led27 led28 led29 led30 led31 led00 led01 led02 led03 led04 led05 . . . . . . lt3746 100k v in 10v to 30v en v cc 3v to 5.5v v in cap 0.47f 16v m1 d1 gate gnd fb isp isn 4.7f 50v 23.2k 10k c1 220f l1 22h 33m 4v maximum output voltage pwmck ttl/cmos m1: vishay si9407bdy d1: diodes dfls160 l1: wrth electronik 7447779122 c1: sanyo 6tpe220mi 409.6khz clock ttl/cmos 3746 ta02 10f 10v 105k 10nf 60.4k 32.4k
lt3746 27 3746f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. p ackage descrip t ion uhh package 56-lead plastic qfn (5mm 9mm) (reference ltc dwg # 05-08-1727 rev a) 5.00 0.10 (2 sides) note: 1. drawing is not a jedec package outline 2. drawing not to scale 3. all dimensions are in millimeters pin 1 top mark (see note 6) 55 1 2 bottom view?exposed pad 3.45 0.10 7.13 0.10 6.80 ref 9.00 0.10 (2 sides) 0.75 0.05 r = 0.115 typ 0.20 0.05 (uh) qfn 0406 rev a 0.40 bsc 0.200 ref 0.200 ref 0.00 ? 0.05 recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 3.60 ref 0.40 0.10 0.00 ? 0.05 0.75 0.05 0.70 0.05 0.40 bsc 6.80 ref (2 sides) 3.60 ref (2 sides) 4.10 0.05 (2 sides) 5.50 0.05 (2 sides) 7.13 0.05 3.45 0.05 8.10 0.05 (2 sides) 9.50 0.05 (2 sides) 0.20 0.05 package outline 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 notch r = 0.30 typ or 0.35 45 chamfer uhh package 56-lead plastic qfn (5mm 9mm) (reference ltc dwg # 05-08-1727 rev a) 56
lt3746 28 3746f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com ? linear technology corporation 2011 lt 0311 ? printed in usa r ela t e d p ar t s typical a pplica t ion part number description comments lt3476 quad output 1.5a, 2mhz high current led driver with 1,000:1 dimming v in : 2.8v to 16v, v out(max) = 36, true color pwm dimming = 1000:1, i sd < 10a, 5mm 7mm qfn-10 package lt3486 dual 1.3a , 2mhz high current led driver v in : 2.5v to 24v, v out(max) = 36, true color pwm dimming = 1000:1, i sd < 1a, 5mm 3mm dfn-16 tssop-16e package lt3496 triple output 750ma, 2.1 mhz high current led driver with 3,000:1 dimming v in : 3v to 30v, v out(max) = 60, true color pwm dimming = 3000:1, i sd < 1a, 4mm 5mm qfn-28 package lt3595 45v, 2.5mhz 16-channel full featured led driver v in : 4.5v to 45v, v out(max) = 45, true color pwm dimming = 5000:1, i sd < 1a, 5mm 9mm qfn-56 package lt3598 44v, 1.5a, 2.5mhz boost 6-channel 30ma led driver v in : 3v to 40v, v out(max) = 44, true color pwm dimming = 1000:1, i sd < 1a, 4mm 4mm qfn-24 package lt3599 44v, 2a, 2.5mhz boost 4-channel 120ma led driver v in : 3v to 40v, v out(max) = 44, true color pwm dimming = 1000:1, i sd < 1a, 4mm 4mm qfn-24 package LT3754 60v, 1mhz boost 16-channel 50ma led driver with true color 3,000:1 pwm dimming and 2.8% current matching v in : 4.5v to 40v, v out(max) = 60, true color pwm dimming = 3000:1, i sd < 1a, 5mm 5mm qfn-32 package lt3755/-1 high side 40v, 1mhz led controller with true color 3,000:1 pwm dimming v in : 4.5v to 40v, v out(max) = 60, true color pwm dimming = 3000:1, i sd < 1a, 3mm 3mm qfn-16 msop-16e package lt3756/-1 high side 100v, 1mhz led controller with true color 3,000:1 pwm dimming v in : 6v to 100v, v out(max) = 100, true color pwm dimming = 3000:1, i sd < 1a, 3mm 3mm qfn-16 msop-16e package lt3760 60v, 1mhz boost 8-channel 100ma led driver with true color 3,000:1 pwm dimming and 2.8% current matching v in : 4.5v to 40v, v out(max) = 60, true color pwm dimming = 3000:1, i sd < 1a, tssop-28e package figure 8. 32-channel led driver, 1mhz buck, 3 leds 10ma to 30ma per channel, 500hz 12-bit dimming en/uvlo sync rt ss v cc i set t set scki sdi ldi scko sdo ldo led29 led30 led31 led00 led01 led02 . . . . . . lt3746 100k v in 13v to 42v en v cc 3v to 5.5v v in cap 0.47f 16v gate gnd fb isp isn 4.7f 50v 80.6k 10k c1 2 47f l1 22h m1 d1 33m 11v maximum output voltage pwmck ttl/cmos 2.048mhz clock ttl/cmos 3746 ta03 10f 10v 46.4k 10nf 60.4k 32.4k m1: vishay si9407bdy d1: diodes dfls160 l1: wrth electronik 7447779122 c1: sanyo 16tqc47m

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